library verilog;
use verilog.vl_types.all;
entity TrafficLight is
    port(
        start           : in     vl_logic;
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        red             : out    vl_logic;
        yellow          : out    vl_logic;
        green           : out    vl_logic;
        cnt             : out    vl_logic_vector(2 downto 0)
    );
end TrafficLight;
